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fea tures ? single power supply operation - low voltage range: 4.5 v - 5.5 v ? memory organization - pm39f010: 128k x 8 (1 mbit) - pm39f020: 256k x 8 (2 mbit) - pm39f040: 512k x 8 (4 mbit) ? high performance read - 55/70 ns access time ? cost effective sector/block architecture - uniform 4 kbyte sectors - uniform 64 kbyte blocks (sector-group) ? data# polling and toggle bit features ? hardware data protection ? automatic erase and byte program - typical 16 s/byte programming time - typical 55 ms sector/block/chip erase time ? low power consumption - typical 8 ma active read current - typical 9 ma program/erase current - typical 0.5 a cmos standby current ? high product endurance - guarantee 100,000 program/erase cycles per single sector (preliminary) - minimum 20 years data retention ? industrial standard pin-out and packaging - 32-pin plastic dip - 32-pin plcc - 32-pin vsop (tsop 8mm x 14mm) - optional lead-free (pb-free) packages general description the pm39f010/020/040 are 1 mbit/2 mbit/4 mbit 5.0 volt-only flash memories. these devices are designed to use a single low voltage, range from 4.5 volt to 5.5 volt, power supply to perform read, erase and program operations. the 12.0 volt v pp power supply for program and erase operations are not required. the devices can be programmed in standard eprom programmers as well. the memory arrays of pm39f010/020/040 are divided into uniform 4 kbyte sectors or uniform 64 kbyte blocks (sector group - consists of sixteen adjacent sectors). the sector or block erase feature allows users to flexibly erase an memory area as small as 4 kbyte or as large as 64 kbyte by one single erase operation without affecting the data in others. the chip erase feature allows the whole memory array to be erased in one single erase opera- tion. the devices can be programmed on a byte-by-byte basis after performing the erase operation. the devices have a standard microprocessor interface as well as a jedec standard pin-out/command set. the program operation is executed by issuing the program command code into command register. the internal control logic automatically handles the programming voltage ramp-up and timing. the erase operation is executed by issuing the chip erase, block, or sector erase command code into command register. the internal control logic automatically handles the erase voltage ramp-up and timing. the preprogramming on the array which has not been programmed is not required before an erase operation. the devices offer data# polling and toggle bit functions, the progress or completion of program and erase operations can be detected by reading the data# polling on i/o7 or the toggle bit on i/o6. the pm39f010/020/040 are manufactured on pmcs advanced nonvolatile cmos technology, p-flash?. the devices are offered in 32-pin pdip, plcc and vsop packages with access time of 55 and 70 ns. pmc 1 mbit / 2 mbit / 4 mbit 5 volt-only cmos flash memory programmable microelectronics corp. issue date: march 2004, rev:1.3 pm39f010 / pm39f020 / pm39f040 1
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 2 20 19 18 17 16 15 14 5 6 7 8 9 10 11 12 13 1 2 3 4323130 29 28 27 26 25 24 23 22 21 a14 a13 a8 a9 a11 oe# a10 ce# i/o7 a14 a13 a8 a9 a11 oe# a10 ce# i/o7 a14 a13 a8 a9 a11 oe# a10 ce# i/o7 i/o1 gnd i/o2 i/o3 i/o4 i/o5 i/o6 i/o1 gnd i/o2 i/o3 i/o4 i/o5 i/o6 i/o1 gnd i/o2 i/o3 i/o4 i/o5 i/o6 i/o0 a0 a1 a2 a3 a4 a5 a6 a7 i/o0 a0 a1 a2 a3 a4 a5 a6 a7 i/o0 a0 a1 a2 a3 a4 a5 a6 a7 a12 a15 v cc we# nc nc a12 a15 v cc we# a12 a15 v cc we# a16 a16 a16 a18 a17 a17 nc 39f010 39f020 39f040 39f040 39f020 39f010 39f010 39f020 39f040 39f040 39f020 39f010 32-pin plcc connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin vsop 39f040 a11 a9 a8 a13 a14 we# v cc a15 a12 a7 a6 a5 a4 a16 a18 a17 39f020 a11 a9 a8 a13 a14 we# v cc nc a15 a12 a7 a6 a5 a4 a16 a17 39f010 a11 a9 a8 a13 a14 we# v cc nc a15 a12 a7 a6 a5 a4 a16 nc i/o4 oe# a10 ce# i/o7 i/o6 i/o5 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 39f040 i/o4 oe# a10 ce# i/o7 i/o6 i/o5 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 39f020 i/o4 oe# a10 ce# i/o7 i/o6 i/o5 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 39f010
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 3 connection diagrams (continued) 32-pin pdip 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 i/o0 i/o1 a1 a0 i/o2 gnd v cc we# nc a14 a13 a8 a9 oe# a10 a11 ce# i/o7 i/o6 i/o5 i/o4 i/o3 39f010 v cc we# a14 a13 a8 a9 oe# a10 a11 ce# i/o7 i/o6 i/o5 i/o4 i/o3 39f020 v cc we# a14 a13 a8 a9 oe# a10 a11 ce# i/o7 i/o6 i/o5 i/o4 i/o3 39f040 a17 a17 39f010 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 i/o0 i/o1 a1 a0 i/o2 gnd 39f020 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 i/o0 i/o1 a1 a0 i/o2 gnd 39f040 8 a0-a ms i/o0-i/o7 ce# oe# we# logic symbol note: a ms is the most significant address where a ms = a16 for pm39f010, a17 for pm39f020, and a18 for pm39f040.
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 4 product ordering informa tion pm39f0x0 -70 j c e temperature range c = commercial (0c to +85c) package type j = 32-pin plastic j-leaded chip carrier (32j) v = 32-pin thin small outline package (32v) p = 32-pin plastic dip (32p) speed option - 70 = 70ns - 55 = 55ns pmc device number pm39f010 (1 mbit) pm39f020 (2 mbit) pm39f040 (4 mbit) environmental attribute e = lead-free (pb-free) package blank = standard package
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 5 part number package temperature range pm39f010-55jce 55 32j commercial (0 o c to + 85 o c) pm39f010-55pce 32p pm39f010-55vce 32v pm39f010-70jce 70 32j pm39f010-70jc pm39f010-70pce 32p pm39f010-70pc pm39f010-70vce 32v pm39f010-70vc pm39f020-55jce 55 32j pm39f020-55pce 32p pm39f020-55vce 32v PM39F020-70JCE 70 32j pm39f020-70jc pm39f020-70pce 32p pm39f020-70pc pm39f020-70vce 32v pm39f020-70vc pm39f040-55jce 55 32j pm39f040-55pce 32p pm39f040-55vce 32v pm39f040-70jce 70 32j pm39f040-70jc pm39f040-70pce 32p pm39f040-70pc pm39f040-70vce 32v pm39f040-70vc tacc(ns)
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 6 pin descriptions l o b m y se p y tn o i t p i r c s e d a - 0 a s m ) 1 ( t u p n i y l l a n r e t n i e r a s e s s e r d d a . t u p n i s e s s e r d d a y r o m e m r o f : s t u p n i s s e r d d a . e l c y c e t i r w a g n i r u d # e w f o e g d e g n i l l a f e h t n o d e h c t a l # e ct u p n i r o f s e i r t i u c r i c l a n r e t n i s ' e c i v e d e h t s e t a v i t c a w o l s e o g # e c : e l b a n e p i h c o t n i s e h c t i w s d n a e c i v e d e h t s t c e l e s e d h g i h s e o g # e c . n o i t a r e p o e c i v e d . n o i t p m u s n o c r e w o p e h t e c u d e r o t e d o m y b d n a t s # e wt u p n i . w o l e v i t c a s i # e w . n o i t a r e p o e t i r w r o f e c i v e d e h t e t a v i t c a : e l b a n e e t i r w # e ot u p n i # e o . e l c y c d a e r a g n i r u d s r e f f u b t u p t u o s ' e c i v e d e h t l o r t n o c : e l b a n e t u p t u o . w o l e v i t c a s i 7 o / i - 0 o / i / t u p n i t u p t u o a t a d t u p t u o r o e l c y c e t i r w a g n i r u d a t a d / d n a m m o c t u p n i : s t u p t u o / s t u p n i a t a d . d e l b a s i d e r a # e o n e h w e t a t s - i r t o t t a o l f s n i p o / i e h t . e l c y c d a e r a g n i r u d v c c y l p p u s r e w o p e c i v e d d n gd n u o r g c nn o i t c e n n o c o n note: 1. a ms is the most significant address where a ms = a16 for pm39f010, a17 for pm39f020, and a18 for pm39f040.
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 7 block diagram device opera tion read operation the access of pm39f010/020/040 are similar to eprom. to read data, three control functions must be satisfied: ? ce# is the chip enable and should be pulled low ( v il ). ? oe# is the output enable and should be pulled low ( v il ). ? we# is the write enable and should remains high ( v ih ) . product identification the product identification mode can be used to identify the manufacturer and the device through hardware or software read id operation. see table 1 for pmc manu- facturer id and device id. the hardware id mode is acti- vated by applying a 12.0 volt on a9 pin, typically used by an external programmer for selecting the right pro- gramming algorithm for the devices. refer to table 2 for bus operation modes. the software id mode is acti- vated by a three-bus-cycle command. see table 3 for software command definition. we# ce# oe# command register ce,oe logic a0-a ms erase/program voltage generator high voltage switch i/o0-i/o7 i/o buffers data latch sense amp y-gating memory array address latch y-decoder x-decoder byte programming the programming is a four-bus-cycle operation and the data is programmed into the devices (to a logical 0) on a byte-by-byte basis. see table 3 for software com- mand definition. a program operation is activated by writ- ing the three-byte command sequence followed by pro- gram address and one byte of program data into the devices. the addresses are latched on the falling edge of we# or ce# whichever occurs later, and the data are latched on the rising edge of we# or ce# whichever occurs first. the internal control logic automatically handles the internal programming voltages and timing. a data 0 can not be programmed back to a 1. only erase operation can convert the 0s to 1s. the data# polling on i/o7 or toggle bit on i/o6 can be used to detect the progress or completion of a program cycle.
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 8 device opera tion (continued) chip erase the entire memory array can be erased through a chip erase operation. pre-programs the devices are not required prior to a chip erase operation. chip erase starts immediately after a six-bus-cycle chip erase command sequence. all commands will be ignored once the chip erase operation has started. the devices will return to standby mode after the completion of chip erase. sector and block erase the memory array of pm39f010/020/040 are organized into uniform 4 kbyte sectors. a sector erase operation allows to erase any individual sector without affecting the data in others. the memory array of those devices are also organized into uniform 64 kbyte blocks (sector group - consists of sixteen adjacent sectors). a block erase operation allows to erase any individual block. the sector or block erase operation is similar to chip erase. i/o7 data# polling the pm39f010/020/040 provide a data# polling feature to indicate the progress or completion of a program and erase cycles. during a program cycle, an attempt to read the devices will result in the complement of the last loaded data on i/o7. once the program operation is com- pleted, the true data of the last loaded data is valid on all outputs. during a sector, block, or chip erase cycle, an attempt to read the device will result a 0 on i/o7. after the erase operation is completed, an attempt to read the device will result a 1 on i/o7. i/o6 toggle bit the pm39f010/020/040 also provide a toggle bit fea- ture to detect the progress or completion of a program and erase cycles. during a program or erase cycle, an attempt to read data from the device will result a tog- gling between 1 and 0 on i/o6. when the program or erase operation is complete, i/o6 will stop toggling and valid data will be read. toggle bit may be accessed at any time during a program or erase cycle. hardware data protection hardware data protection protects the devices from un- intentional erase or program operation. it is performed in the following ways: (a) v cc sense: if v cc is below 3.8 v (typical), the write operation is inhibited. (b) write inhibit: holding any of the signal oe# low, ce# high, or we# high inhibits a write cycle. (c) noise filter: pulses of less than 5 ns (typical) on the we# or ce# input will not initiate a write operation. n o i t a c i f i t n e d i t c u d o r pa t a d d i r e r u t c a f u n a mh d 9 : d i e c i v e d 0 1 0 f 9 3 m ph c 1 0 2 0 f 9 3 m ph d 4 0 4 0 f 9 3 m ph e 4 table 1. product identification
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 9 y t i s n e d y r o m e mk c o l b ) 1 ( e z i s k c o l b ) s e t y b k ( r o t c e s e z i s r o t c e s ) s e t y b k ( e g n a r s s e r d d a t i b m 1 t i b m 2 t i b m 4 0 k c o l b4 6 0 r o t c e s4 h f f f 0 0 - h 0 0 0 0 0 1 r o t c e s4 h f f f 1 0 - h 0 0 0 1 0 :: : 5 1 r o t c e s4 h f f f f 0 - h 0 0 0 f 0 1 k c o l b4 6 6 1 r o t c e s4 h f f f 0 1 - h 0 0 0 0 1 7 1 r o t c e s4 h f f f 1 1 - h 0 0 0 1 1 :: : 1 3 r o t c e s4 h f f f f 1 - h 0 0 0 f 1 2 k c o l b4 6 "" h f f f f 2 - h 0 0 0 0 2 3 k c o l b4 6 "" h f f f f 3 - h 0 0 0 0 3 4 k c o l b4 6 "" h f f f f 4 - h 0 0 0 0 4 5 k c o l b4 6 "" h f f f f 5 - h 0 0 0 0 5 6 k c o l b4 6 "" h f f f f 6 - h 0 0 0 0 6 7 k c o l b4 6 "" h f f f f 7 - h 0 0 0 0 7 sect or/block address t able note: 1. a block is a 64 kbyte sector group which consists of sixteen adjecent sectors of 4 kbyte each.
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 10 command definition table 3. software command definition d n a m m o c e c n e u q e s s u b e l c y c s u b t s 1 e l c y c a t a d r d d a s u b d n 2 e l c y c a t a d r d d a s u b d r 3 e l c y c a t a d r d d a s u b h t 4 e l c y c a t a d r d d a s u b h t 5 e c l y c a t a d r d d a s u b h t 6 e l c y c a t a d r d d a d a e r1d r d d a t u o e s a r e p i h c6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2h 0 1 h 5 5 5 e s a r e r o t c e s6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2a s ) 1 ( h 0 3 e s a r e k c o l b6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2a b ) 2 ( h 0 5 m a r g o r p e t y b4h a a h 5 5 5h 5 5 h a a 2h 0 a h 5 5 5d r d d a n i y r t n e d i t c u d o r p3h a a h 5 5 5h 5 5 h a a 2h 0 9 h 5 5 5 t i x e d i t c u d o r p ) 3 ( 3h a a h 5 5 5h 5 5 h a a 2h 0 f h 5 5 5 t i x e d i t c u d o r p ) 3 ( 1h 0 f h x x x notes: 1. sa = sector address of the sector to be erased. 2. ba = block address of the block to be erased. 3. either one of the product id exit command can be used. opera ting modes notes: 1. x can be v il , v ih or addresses. 2. a ms = most significant address; a ms = a16 for pm39f010, a17 for pm39f020, and a18 for pm39f040. table 2. bus operation modes e d o m# e c# e o# e ws s e r d d ao / i d a e rv l i v l i v h i x ) 1 ( d t u o e t i r wv l i v h i v l i xd n i y b d n a t sv h i xx x z h g i h e l b a s i d t u p t u oxv h i xx z h g i h n o i t a c i f i t n e d i t c u d o r p e r a w d r a h v l i v l i v h i a - 2 a s m ) 2 ( == 9 a , x v h ) 3 ( , v = 1 a l i v = 0 a , l i d i r e r u t c a f u n a m a - 2 a s m ) 2 ( = 9 a , x = v h ) 3 ( , v = 1 a l i v = 0 a , h i d i e c i v e d 3. v h = 12.0 v 0.5 v.
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 11 device opera tions flowcharts automatic programming chart 1. automatic programming flowchart start load data aah to address 555h load data 55h to address 2aah load data a0h to address 555h load program data to program address i/o7 = data? or i/o6 stop toggle? last address? programming completed no no yes yes address increment
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 12 automatic erase chart 2. automatic erase flowchart device opera tions flowcharts (continued) start write sector, block, or chip erase command data = ffh? or i/o6 stop toggle? erasure completed yes no sector erase command load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 10h to address 555h load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 30h to sa chip erase command block erase command load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 50h to ba
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 13 software product identification exit load data aah to address 555h load data 55h to address 2aah load data 90h to address 555h enter product identification mode (1,2) load data aah to address 555h load data 55h to address 2aah load data f0h to address 555h exit product identification mode (3) load data f0h to address xxxh exit product identification mode (3) or chart 3. software product identification entry/exit flowchart software product identification entry device opera tions flowcharts (continued) notes: 1. the device will enter product identification mode after excuting the product id entry command. 2. under product identification mode, the manufacturer id and device id of devices can be read at address x0000h and x0001h where x = dont care. 3. the device returns to standby operation.
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 14 dc and ac opera ting range absolute maximum ra tings (1) notes: 1. stresses under those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. the functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. maximum dc voltage on input or i/o pins are +6.25 v. during voltage transitioning period, input or i/o pins may overshoot to v cc + 2.0 v for a period of time up to 20 ns. minimum dc voltage on input or i/o pins are - 0.5 v. during voltage transitioning period, input or i/o pins may undershoot gnd to -2.0 v for a period of time up to 20 ns. 3. maximum dc voltage on a9 pin is +13.0 v. during voltage transitioning period, a9 pin may overshoot to +14. 0 v for a period of time up to 20 ns. minimum dc voltage on a9 pin is -0.5 v. during voltage transitioning period, a9 pin may undershoot gnd to -2.0 v for a period of time up to 20 ns. temperature under bias -65 o c to +125 o c storage temperature -65 o c to +125 o c surface mount lead soldering temperature standard package 240 o c 3 seconds lead-free package 260 o c 3 seconds input voltage with respect to ground on all pins except a9 pin (2) -0.5 v to +6.25 v input voltage with respect to ground on a9 pin (3) -0.5 v to +13.0 v all output voltage with respect to ground -0.5 v to v cc + 0.6 v v cc (2) -0.5 v to +6.25 v part number pm39f010/020/040 operating temperature 0 o c to 85 o c vcc power supply 4.5 v - 5.5 v
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 15 dc characteristics read operations characteristics ac characteristics note: 1. characterized but not 100% tested. symbol parameter condition min typ max units i li input load current v in = 0 v to v cc +1 i lo output leakage current v i/o = 0 v to v cc +1 i sb1 v cc standby current cmos ce#, oe# = v cc ?0.5 v 0.5 10 i sb2 v cc standby current ttl ce# = v ih to v cc 0.2 3 ma i cc1 v cc active read current f = 5 mhz; i out = 0 ma 8 20 ma i cc2 (1) v cc program/erase current 9 20 ma v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 5.8 ma; v cc = v cc min 0.45 v v oh output high voltage i oh = -400 m a; v cc = v cc min 2.4 v m a m a m a symbol parameter pm39f010-55 pm39f020-55 pm39f040-55 pm39f010-70 pm39f020-70 pm39f040-70 units min max min max t rc read cycle time 55 70 ns t acc address to output delay 55 70 ns t ce ce# to output delay 55 70 ns t oe oe# to output delay 25 35 ns t df ce# or oe# to output high z 0 15 0 25 ns t oh output hold from oe#, ce# or address, whichever occured first 00ns t vcs v cc set-up time 50 50 m s
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 16 read operations ac waveforms output test load input test waveforms and measurement level ac characteristics (continued) pin capacitance ( f = 1 mhz, t = 25c ) p y tx a ms t i n us n o i t i d n o c c n i 46 f pv n i v 0 = c t u o 82 1f pv t u o v 0 = note: these parameters are characterized but not 100% tested. address valid t rc t acc t ce t oe t df t oh output valid high z address ce# oe# we# output v cc t vcs 5.0 v 1.8 k 1.3 k output pin c l = 30 pf 3.0 v 0.0 v 1.5 v ac measurement level input
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 17 write (program/erase) operations characteristics ac characteristics (continued) program operations ac waveforms - we# controlled t ch t cs t wp t wph t bp t dh t ds t ah t as 555 555 address 2aa aa 55 a0 input data valid data data in a0 - a ms oe# we# ce# pro g ram cycle t wc v cc t vcs symbol parameter pm39f010-55 pm39f020-55 pm39f040-55 pm39f010-70 pm39f020-70 pm39f040-70 units min max min max t wc write cycle time 55 70 ns t as address set-up time 0 0 ns t ah address hold time 30 30 ns t cs ce# and we# set-up time 0 0 ns t ch ce# and we# hold time 0 0 ns t oeh oe# high hold time 10 10 ns t ds data set-up time 30 30 ns t dh data hold time 0 0 ns t wp write pulse width 30 35 ns t wph write pulse width high 20 20 ns t bp byte programming time 30 30 t ec chip or block erase time 100 100 ms t vcs v cc set-up time 50 50 m s m s
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 18 ac characteristics (continued) chip erase operations ac waveforms t ch t cs t wp t wph t bp t dh t ds t ah t as 555 555 address 2aa aa 55 a0 input data valid data data in a0 - a ms oe# we# ce# program cycle t wc v cc t vcs program operations ac waveforms - ce# controlled aa 55 55 10 80 aa 555 2aa 555 555 2aa t ec t wph t wp t as t ah t dh t ds ao - a ms we# ce# oe# data in t wc 555 v cc t vcs
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 19 sector or block erase operations ac waveforms aa 55 55 30 or 50 80 aa 555 2aa 555 555 2aa sector or block address t ec t wph t wp t as t ah t dh t ds ao - a ms we# ce# oe# data in t wc v cc t vcs toggle bit ac waveforms ac characteristics (continued) t oeh we# ce# oe# i/o6 toggle stop toggling valid data t oe toggle data t df t oh note: toggling ce#, oe#, or both oe# and ce# will operate toggle bit.
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 20 data# polling ac waveforms ac characteristics (continued) note: toggling ce#, oe#, or both oe# and ce# will operate data# polling. program/erase performance t ch t ce t oeh t oe t df t oh valid data i/o7# we# ce# oe# i/o7 r e t e m a r a pt i n up y tx a ms k r a m e r e m i t e s a r e r o t c e ss m5 50 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t e s a r e k c o l bs m5 50 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t e s a r e p i h cs m5 50 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t g n i m m a r g o r p e t y b m s 6 10 3 d n a m m o c m a r g o r p e l c y c - r u o f f o e m i t e h t s e d u l c x e n o i t u c e x e r e t e m a r a pn i mp y tt i n ud o h t e m t s e t e c n a r u d n e0 0 0 , 0 0 1 ) 2 ( s e l c y c7 1 1 a d r a d n a t s c e d e j n o i t n e t e r a t a d0 2s r a e y3 0 1 a d r a d n a t s c e d e j l e d o m y d o b n a m u h - d s e0 0 0 , 2s t l o v4 1 1 a d r a d n a t s c e d e j l e d o m e n i h c a m - d s e0 0 2s t l o v5 1 1 a d r a d n a t s c e d e j p u - h c t a l i + 0 0 1 1 c c a m8 7 d r a d n a t s c e d e j note: these parameters are characterized but not 100% tested. note: 1. these parameters are characterized but not 100% tested. 2. preliminary specification only and will be formalized after cycling qualification test. reliability characteristics (1)
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 21 p ackage type informa tion 32j 32-pin plastic leaded chip carrier dimensions in inches (millimeters) 32p 32-pin plastic dip dimensions in inches (millimeters) pin 1 i.d. 15.11 14.86 14.05 13.89 1.27 typ. 0.81 0.66 11.51 11.35 12.57 12.32 0.74x30 13.46 12.45 0.53 0.33 2.41 1.93 3.56 3.18 seating plane seating plane .150 .120 .110 .090 .022 .016 .200 .170 .050 .015 .625 .600 .012 .008 0 10 .665 .625 1.655 1.645 17 32 16 pin 1 i.d. .550 .530 .065 .040 .005 min
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 22 p ackage type informa tion (continued) 32v 32-pin thin small outline package (tsop 8mm x 14mm)(millimeters) 0.50 bsc 1.05 0.95 0.27 0.17 0.15 0.05 pin 1 i.d. 12.50 12.30 14.20 13.80 8.10 7.90 1.20 max 0.25 0 5 0.20 0.10 0.70 0.50
programmable microelectronics corp. issue date: march, 2004, rev: 1.3 pmc pm39f010 / pm39f020 / pm39f040 23 revision hist or y e t a d. o n n o i s i v e rs e g n a h c f o n o i t p i r c s e d. o n e g a p 3 0 0 2 , h c r a m0 . 1n o i t a m r o f n i y r a n i m i l e r pl l a 3 0 0 2 , t s u g u a1 . 1 l a m r o f d n a e d a r g d e e p s d a e r s n 0 9 d e v o m e r 6 . p n o o p y t d e x i f ; e s a e l e r 6 1 , 5 1 , 4 1 , 4 , 1 3 0 0 2 , r e b m e c e d2 . 1 s n o i t p o e g a k c a p e e r f - d a e l d e d d a3 1 , 4 , 1 m o r f s e l c y c e s a r e / m a r g o r p d e e t n a r u g d e d a r g p u ) y r a n i m i l e r p ( 0 0 0 , 0 0 1 o t 0 0 0 , 0 5 9 1 , 1 d e e p s l l a r o f f p 0 3 o t d a o l t s e t t u p t u o d e s i v e r5 1 n o i t a m r o f n i n o i s n e m i d e g a k c a p n o o p y t d e s i v e r1 2 , 0 2 4 0 0 2 , h c r a m 3 . 1 e r u t a r e p m e t f o e g n a r n o i t a r e p o e h t d n e t x el l a

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